A backplane, usually constructed as a printed circuit, is used in a computer to provide the required connections between logic, memory, and input/output modules. FIG. 1 schematically depicts a typical backplane circuit 10 comprising a main transmission line having a characteristic impedance of 50 .OMEGA. and a plurality of stubs (denoted "L1" through "L8") each having a characteristic impedance of 80 .OMEGA.. Eight circuit cards (not shown) may be coupled to the backplane via the eight stubs. The stubs in this example are positioned at intervals of one to two inches. The ends of the main transmission line are terminated with resistive loads. In practice, the backplane 10 is composed of generally similar conductive traces formed on a suitable substrate to form an N-bit wide bus, where N is determined by the computer architecture.
Any circuit coupled to the backplane 10 would employ a driver and/or receiver (or transceiver) as an interface between the circuit and the backplane. Transmit-only or output-only devices employ a driver whereas receive-only or input-only devices employ a receiver. Input/output devices employ a transceiver. The present invention particularly relates to a backplane driver, although it may be employed in a transceiver.
Digital computers and the like often include VLSI circuits which are interconnected for binary communications by a single segment or multi-segment transmission line. Drivers and receivers interface the VLSI components of such systems to the transmission line. The transmission line typically is formed by a microstrip trace or strip line having a characteristics impedance on the order of 50-70 .OMEGA.. A standard practice is to terminate the opposite ends of the main transmission line in its characteristic impedance. Thus, the output load on a driver for such a transmission line may be as low as 25 .OMEGA. to 40 .OMEGA. (i.e., the effective resistance of the parallel resistive terminations for the backplane).
The power internally dissipated by a driver is proportional to the nominal voltage swing of the binary signal it applies to the backplane and to the nominal low voltage limit of that signal (i.e., the logical "0" level). CMOS technology is attractive for fabricating VLSI circuits having relatively high gate densities, but the nominal 5 V rail-to-rail voltage swing (nominally, 0 V to 5 V) of standard CMOS circuits tends to cause the output drivers for such circuits to dissipate excessive power whenever the drivers are working into low impedance loads, such as a terminated transmission line of the above-described type. In recognition of that problem, voltage buffering drivers and voltage translating receivers for interfacing CMOS circuits to transmission lines have been proposed. Particularly, proposals have been made for carrying out binary communications at TTL (transistor-transistor logic) signal levels (nominally 0 V to 3.5 V), at PECL (positive emitter coupled logic) signal levels (nominally, 3.2 V to 4.2 V), and at BTL (backplane transistor logic) signal levels (nominally, 1.1 V to 2.0 V). PECL and BTL signaling dissipates less power than TTL signaling. However, PECL and BTL signaling are relatively difficult to implement in CMOS. TTL signaling is easier to implement in CMOS but, from a power dissipation standpoint, TTL signalling provides only a modest improvement over rail-to-rail CMOS signaling.
U.S. Pat. No. 5,023,488, Jun. 11, 1991, titled "Drivers and Receivers for Interfacing VLSI CMOS Circuits to Transmission Lines," discloses an N-channel CMOS driver and cascode CMOS receiver for interfacing VLSI CMOS circuits to transmission lines terminated by their characteristic impedances to voltage levels on the order of 1.2 to 2.0 V. These "GTL" (Gunning Transceiver Logic) drivers and receivers purportedly operate with a voltage swing on the order of about 0.8 V-1.4 V in carrying out binary communications between CMOS circuits configured to operate with standard 5 V rail-to-rail voltage swings for their internal signals. This patent discusses the use of GTL drivers and receivers with a transmission line terminated at its opposite ends, but not with a backplane having stubs connected to the main transmission line.
FIG. 2 schematically depicts how a GTL transceiver 12 would be coupled to a backplane 10 with stubs (the backplane 10 is not shown in FIG. 2). The GTL transceiver 12 comprises a GTL driver 14 and a GTL receiver 16. Supply voltages V.sub.DD and V.sub.SS are maintained on package pins 18 and 20, respectively. The GTL transceiver 12 is coupled to backplane 10 through a signal package pin 22, substrate via hole 24, stub 26, via 28, and connector 30. The stub 26 may be, e.g., a 1.5-inch, 80 .OMEGA. microstrip transmission line.
FIG. 3 is a simplified schematic diagram of the GTL driver 14. The driver 14 comprises an P-channel FET 14-1, N-channel FETs 14-2 through 14-5, inverters 14-6 and 14-7, a terminal ("DATAOUT") for receiving the signal to be output, and an output terminal or pin ("PAD"). This circuit provides an open drain output with feedback (transistors 14-4 and 14-5) to control inductive overshoot caused by quickly turning off transistor 14-3. The feedback is turned on when the output signal ("DATAOUT") switches to a high state, turning transistor 14-4 on while transistor 14-5 is already on. The feedback is intended to reduce the overshoot during a low to high transition on the signal output pin ("PAD"). Therefore, the feedback is left on only for a brief period. This period is determined by the propagation delay through inverters 14-6 and 14-7.
The present inventors have discovered that using the GTL driver in a backplane environment results in signal integrity problems when the output is switched from a low to a high state (as in FIGS. 5A and 5B, discussed below). Such problems are due to reflections resulting from mismatched impedances. (It should be noted that the GTL driver works well in an environment that has a main trace only with no stubs.) The standard GTL circuit attempts to address this signal integrity problem with a feedback path (transistors 14-4 and 14-5 in FIG. 3) that tends to turn the driver back on if the output goes above a certain voltage. This circuit is effective in controlling problems caused by the inductive effects that result from quickly turning off the output transistor (14-3 in FIG. 3). This is the primary cause of signal integrity problems in an environment with no stubs. However, in a backplane environment or any other environment with a main transmission lines and stubs of significant length, signal integrity problems will also be caused by reflections from the stubs. The standard GTL circuit is ineffective in this environment. The modified GTL driver circuit disclosed in this specification was developed to overcome this problem.